| Title |
Chemical?Mechanical Polishing Challenges and Dishing Control in Hybrid Cu/SiO2 Bonding for Advanced 3D Packaging: A Review |
| Authors |
이수(Su Lee) ; 김현식(Hyun-Sik Kim) ; 정도현(Do Hyun Jung) ; 정재필(Jae Pil Jung) |
| DOI |
https://doi.org/10.3365/KJMM.2026.64.4.350 |
| ISSN |
1738-8228(ISSN), 2288-8241(eISSN) |
| Keywords |
Artificial intelligence; Semiconductor packaging; Hybrid bonding; Chemical mechanical polishing; Copper dishing |
| Abstract |
Copper and silicon dioxide (Cu-SiO2) hybrid bonding is a pivotal technology for realizing ultra-fine
pitch and high-density input/output (I/O) in 3D semiconductor packaging, specifically for artificial intelligence
(AI) and high-performance computing (HPC) applications. However, the chemical mechanical polishing (CMP)
process, critical for planarization, inherently suffers from dishing. This defect is driven by the significant
disparity in material removal rates between ductile Cu pads and the surrounding rigid dielectric, leading to
excessive Cu recession. Dishing is a critical failure mode that jeopardizes device reliability. It not only creates
interfacial voids that impede atomic diffusion bonding but also exacerbates thermal stress concentration due
to the coefficient of thermal expansion (CTE) mismatch during post-annealing. These topographical
imperfections can lead to severe cracking and delamination. To mitigate these challenges, this paper provides
a systematic review of dishing mechanisms and control strategies across three dimensions: process, material,
and design. In process optimization, we highlight advanced slurry formulations, such as Fenton reactionbased
chemistries, and multi-step CMP techniques capable of correcting surface topography. Regarding
materials, the transition from SiO2 to silicon carbonitride (SiCN) is analyzed for its superior mechanical
hardness and erosion resistance. Furthermore, design-based solutions, specifically the insertion of dummy
patterns to ensure uniform pattern density and minimize the loading effect, are discussed. This
comprehensive review provides actionable guidelines for achieving nanometer-level surface control, ensuring
the yield and reliability of next-generation heterogeneous integration. |